Method of manufacturing a semiconductor device having narrow coplanar silicon electrodes

ABSTRACT

A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.

The invention relates to a method of manufacturing a semiconductordevice comprising a plurality of adjacent narrow and closely spacedcoplanar silicon electrodes in which on an electrically insulating layerthere are deposited successively a first silicon layer anoxidation-preventing layer and a second silicon layer, after which thesecond silicon layer is etched in a pattern comprising a plurality ofparallel silicon strips whereupon this silicon pattern is partlyoxidized and the uncovered parts of the oxidation-preventing layer arethen removed by etching, after which the oxide present is etched away,the second silicon layer and the uncovered parts of the first siliconlayer are thermally oxidized, the uncovered parts of theoxidation-preventing layer are removed by selective etching and apattern comprising parallel silicon electrodes separated by grooves isformed by etching away the subjacent parts of the first silicon layer.

The invention further relates to a semiconductor device manufactured bymeans of the method.

A method of the kind described above is known from the published BritishPatent Application GB-A No. 2,111,304 of the Applicant. This Applicationdescribes the manufacture of a charge-coupled (CCD) semiconductordevice, in which in a self-registered manner control electrodes ofsilicon are formed, whose very small spacing of, for example, less than1 μm is determined by lateral oxidation of a silicon pattern.

In this manner, overlapping control electrodes and hence a double-layerelectrode system can be avoided, which has great advantages intechnological and electrical respect.

However, problems often arise when contacting a large number of verynarrow and closely spaced electrodes. Since it is difficult to providecontacts on very narrow electrodes, the electrodes can be made to extendat one or both ends outwards in the form of a fan, but this requiresspace. Furthermore, the silicon electrodes have to be provided inmutually separated groups, for which purpose interruptions will have tobe formed in the said first silicon layer. According to the methoddescribed in GB-A No. 2,111,304, this is effected in that at the areasat which there must not be present a silicon layer in the finisheddevice, the second silicon layer is converted already at the beginningof the process throughout its thickness into silicon oxide. However,this requires an additional masking and oxidation step. The saidinterruptions in the first silicon layer then are formed automaticallyduring the processing step in which the grooves are formed between thestrip-shaped silicon electrodes.

The invention has inter alia for its object to provide a method in whichthe said problems are avoided and in which a monolayer electrodeconfiguration of high density can be obtained without an additionalmask.

The invention is based inter alia on the recognition of the fact thatthis can be achieved in that the said interruptions are provided in thefirst silicon layer during a processing step other than that in whichthe grooves are formed between the silicon electrodes.

According to the invention, a method of the kind described in theopening paragraph is characterized in that at least two of the so formedsilicon electrodes which are covered by the oxidation-preventing layerare interconnected by means of a part of the first silicon layer, inthat this connection is interrupted by a masking and etching step, inthat the uncovered parts of the first silicon layer are thermallyoxidized until the grooves are entirely filled at least in part withoxide and in that by selectively locally etching the oxidationpreventing layer contact windows are formed on the underlying siliconelectrodes.

In the method according to the invention, no local oxidation of thesecond silicon layer is necessary before patterning this layer so thatat the beginning of the process a masking and oxidation step is avoided.Furthermore, when the grooves are oxidized at the end of the process apart of the contact windows can be provided in a self-aligned manner atleast in one direction by selectively etching away theoxidation-preventing layer, as will be described in detail hereinafter.As a result, inter alia memory cells having very small dimensions can beobtained.

According to a preferred embodiment, the first silicon layer used is ahighly doped layer and the second silicon layer used is a considerablymore weakly doped layer. The difference in rate of oxidation between thehighly doped silicon layer oxidizing more rapidly and the more weaklydoped second silicon layer oxidizing more slowly can then be utilized ina suitable manner. The highly doped first layer is for this purposepreferably n-type conducting and has a doping concentration of at least2.10.sup.° donor atoms/cm³.

According to another preferred embodiment, in which it is not necessaryfor a difference in rate of oxidation to exist between the first and thesecond silicon layer, the second silicon layer is thinner than the firstsilicon layer and a second oxidation-preventing layer is formed on thesecond silicon layer, as a result of which the pattern formed from thesecond silicon layer is partly oxidized only at the edge of this layer,after which the second oxidation-preventing layer is removed.Subsequently, the second silicon layer is preferably converted entirelyand the first silicon layer is converted only in part into oxide,whereupon the oxide formed from the second silicon layer is removed by adip-etching step, the oxide formed on the first silicon layer remainingpartly in tact.

The oxidation-preventing layers used preferably comprise silicon nitrideand consist, for example, of silicon oxynitride or silicon nitride.

The invention further relates to a semiconductor device manufactured bythe use of the method described. The invention more particularly relatesto a field effect device having a plurality of adjacent gate electrodesin the form of narrow coplanar silicon strips which are formed from asingle silicon layer and which alternately belong to a first groupcovered by silicon oxide and to a second group covered by an insulatinglayer comprising silicon nitride, the gate electrodes being separatedfrom each other by the silicon oxide covering the first group, and thegate electrodes of the second group being formed by separatingoriginally pairwise coherent silicon strips, wherein the gate electrodesare contacted via contact windows, and the contact windows of the gateelectrodes of the second group in the direction of the charge transportare bounded by the silicon oxide covering the gate electrodes of thefirst group.

The invention is of particular importance in the case in which thesemiconductor device is a series/parallel/series (SPS) memory. Due tothe compact construction, very small memory cells, for example of lessthan 20 μm² surface area or even smaller, can be obtained.

The invention will now be described more fully with reference to anembodiment and the drawing, in which:

FIG. 1 is a plan view of a part of a semiconductor device manufacturedusing the method according to the invention,

FIG. 2 shows diagrammatically a cross-sectional view of the device ofFIG. 1 taken on the line II--II,

FIG. 3 shows diagrammatically a cross-sectional view of the device ofFIG. 1 taken on the line III--III,

FIG. 4 shows diagrammatically a cross-sectional view of the device ofFIG. 1 taken on the line IV--IV,

FIGS. 2A to 2F and 3A to 3F show successive stages in the manufacture ofthe device of FIG. 1 in cross-sectional views taken on the lines II--IIand III--III, respectively,

FIG. 5 is a plan view of another part of the device of FIG. 1,

FIG. 6 shows diagrammatically the variation of the clock voltages of theparallel register of the device shown in FIG. 1, and

FIGS. 7A to F show diagrammatically in cross-sectional view successivestages in the manufacture of the device shown in FIG. 1 according to avariation of the method in accordance with the invention.

The Figures are purely schematic and not drawn to scale. Correspondingparts are generally denoted by the same reference numerals.

FIG. 1 shows in plan view and FIGS. 2, 3 and 4 show in cross-sectionalviews taken on the lines II--II, III--III and IV--IV of FIG. 1 a part ofa semiconductor device manufactured by means of the method according tothe invention. The semiconductor device in this example is acharge-coupled device, also designated as CCD, which has the form of aso-called SPS (Series/Parallel/Series) memory. It consists of a seriesregister (designated by the arrow S) controlled by a number ofstrip-shaped silicon electrodes 3A, B located on a thin insulating layer2A, and can displace charge carriers in a subjacent silicon region 1along the surface according to the arrow S along the line II--II. Thecontents of this series register can be transferred in a usual manner bymeans of the gate electrodes 13A,B to a second series register (notshown) which extends parallel to S and from which the informationoriginally stored in S can be read. The shift registers S and P arelocated inside a sunken oxide pattern 2 (in FIG. 1 limited by the line20).

This semiconductor device is manufactured in accordance with theinvention in the manner indicated in FIGS. 2A to 2F and 3A to 3F for thecross-sections taken on the lines II--II and III--III, respectively.

The starting material is a semiconductor substrate, in this exampleconstituted by a p-type conducting silicon layer 1 having, for example,a thickness of 5 μm and a doping concentration of 5.10¹⁴ atoms/cm³,which is grown epitaxially on a highly doped p-type silicon substrate11. In known manner, a countersunk pattern 2 of silicon oxide (limitedin FIG. 1 by the line 20) having a thickness of about 0.5 μm is providedin the layer 1 by local selective oxidation, while the silicon layer 1is covered outside this countersunk pattern 2 by an oxide layer 2Ahaving, for example, a thickness of 50 nm (see FIGS. 2-4, 2A and 3A).

In known manner, there are deposited successively on the insulatinglayer (2,2A) a first silicon layer 3, an oxidation-preventing layer 4(in this example a silicon nitride layer) and a second silicon layer 5.The layer 4 may also consist of another material comprising siliconnitride, for example silicon oxynitride. The silicon layers are mostlydeposited in the form of a polycrystalline layer.

In this example the first silicon layer 3 is a 0.5 μm thick n-type layerhaving a doping concentration of 7.10²⁰ atoms/cm³. Its doping can beeffected either simultaneously with the deposition or after this step bymeans of diffusion or ion implantation.

In this example, the second silicon layer 5 is undoped, that is to saythat it is not doped intentionally, and has a thickness of 0.7 μm. Thelayer 5 is an auxiliary layer, which is removed at the end of theprocess.

In a usual manner, by masking and etching, the second silicon layer 5 isgiven a pattern which comprises a number of parallel silicon stripsseparated from each other by strip-shaped interstices (see FIGS. 2A and3A). The longitudinal direction of these strips is at right angles tothe plane of the drawing.

Subsequently, this silicon pattern is partly oxidized, an oxide layer 6being formed in this process (see FIGS. 2B and 3B). This oxidation maybe carried out, for example, in wet oxygen at a temperature of 1000° C.for 3 hours. The oxide layer 6 then has a thickness of about 0.5 μm.

Subsequently, the uncovered parts of the silicon nitride layer 4 areremoved by etching. This may be effected, for example, in hotconcentrated phosphoric acid or by plasma-etching (see FIGS. 2C and 3C).

The oxide 6 present is then etched away. Thereafter the second siliconlayer 5 and the now uncovered parts of the first silicon layer 3 arethermally oxidized. A thick oxide layer 8 is formed on the highly dopedsilicon layer 3, while a considerably thinner oxide layer 7 is formed onthe substantially undoped silicon layer 5 (see FIGS. 2D and 3D).

Subsequently, this thin oxide layer 7 is removed by a dip-etching step.By selective etching in, for example, hot phosphoric acid, the uncoveredparts of the silicon nitride layer 4 are now removed. Thereafter, apattern comprising parallel silicon electrodes 3A, B; 13A, B separatedby grooves 14 is formed by etching away the subjacent parts of the firstsilicon layer 3. Moreover, the remaining parts of the second siliconlayer 5 are removed. Thus, the structure of FIGS. 2E and 3E is obtained,in which the electrodes 3A, 13A are covered by oxide and the electrodes3B, 13B are covered by nitride.

According to the invention, after this operation, at least two siliconelectrodes 3B1, 3B2 and 13B1, 13B2, respectively, covered by siliconnitride are still interconnected by a part 3C, 13C of the first siliconlayer 3 (see FIG. 1).

In order to interrupt these connections 3C, 13C, a photolacquer mask 9is now provided (see FIGS. 2E and 3E). By etching away the part of theoxide layer 8 left free by this mask and the subjacent silicon layer 3,the connections 3C, 13C are interrupted. Subsequently, in the presenceof the photolacquer mask 9, the desired n-type source and drain zones 17are implanted at the unmasked areas not occupied by the countersunkoxide pattern 2 (see FIGS. 1, 2E and 2F). The mask 9 is then removed andthe uncovered parts of the silicon layer 3 are thermally oxidized untilthe grooves 14 are partly or entirely filled by oxide 10 (FIGS. 2F, 3F).The remaining parts of the silicon electrodes covered by nitride arecross-hatched in the plan views of FIGS. 1 and 5.

The mask 9 defines both the electrode ends and the source and drainzones. Instead of after the formation of the mask 9, the grooves mayalso be closed by oxidation before this operation.

By selectively locally etching the oxidation-preventing silicon nitridelayer 4, contact windows 15 are now formed on the subjacent siliconelectrodes 3B, 13B (see FIGS. 1 and 4). In the plan views, the contactwindows are indicated by diagonal lines. Since the contact windows 15are limited in the direction of the arrow S (FIG. 1) by the oxide 10,they can be provided in a self-aligned manner at least in thatdirection.

Contact windows (16) are also formed on a part of the silicon electrodes3A covered by oxide 10. However, a sufficient amount of space isavailable for this purpose in the widened end of the electrodes 3A sothat these contact windows can be provided without self-alignment.

Via the contact windows, the silicon electrodes 3A and 3B are thenconnected to conductor tracks 18, which can be connected to the desiredgate voltage. For the sake of simplicity, these conductor tracks (seeFIGS. 3 and 4) are omitted in the plan views of FIGS. 1 and 5.

Electrodes that have to be connected to the same gate or clock voltage,are preferably interconnected. For one group of such electrodes, thesilicon layer 3 itself can be used for this purpose. In this example,this is the case for the electrodes 3A1, 3A2 etc., which (see FIG. 1)are interconnected by the part 3D of the silicon layer 3, which part isprovided with a connection conductor in the contact window 19.

In order to be able to transfer the charges from the series register Sto the parallel registers P, a transfer electrode 12 is provided betweenS and P. This electrode, which may be made, for example, of aluminium,is the only electrode which is not formed from the first silicon layer3.

The series register S is suitable with the electrode configuration ofthis example to be controlled with four clock voltages S₁, S₂, S₃ andS₄, which are applied to the electrodes, as is indicateddiagrammatically in FIG. 1.

The parallel registers P have an electrode configuration as shown inpart in plan view in FIG. 5. A high charge density can be attained whenthe drive is effected, as in this example, in eight phases with clockvoltages P₁ to P₈, which are connected as shown in FIG. 5, with four"storage" electrodes (P₁, P₃, P₅, P₇) and four "transfer" electrodes(P₂, P₄, P₆, P₈). Half the number of electrodes is connected on thelefthand side and the other half is connected to the righthand side ofthe parallel registers P. The cross-hatched silicon electrodes coveredby silicon nitrides are separated from each other by interruptions atthe boundaries 30, 31 and 32, which interruptions are formed during theprocessing step shown in the cross-sections of FIGS. 2F and 3F.

The information supplied by the parallel registers P is read out by aseries register provided at the other end of these registers. Thisseries register may have the same construction as the series registerand S and is not shown here further.

When in the structure described use is made of silicon strips having awidth of, for example, 1.5 μm, memory cells having a surface area of 9μm² can be obtained (see the dotted rectangle 33 in FIG. 5). The clockvoltages used for operating the parallel registers P are showndiagrammatically in FIG. 6 as a function of the time t.

The device described above may also be manufactured without usingsilicon layers having greatly different doping concentrations. However,this requires a second oxidation-preventing layer. FIGS. 7A to 7E showsuccessive stages of such a manufacture, the cross-sections being takenon the same plane II--II as those of FIGS. 2 and 2A to 2F.

There are now provided on the oxide layer 2A and the countersunk oxidepattern 2 (not lying in the cross-section of FIG. 7) a first siliconlayer 3, a first oxidation-preventing layer 4, a second silicon layer 5and a second oxidation-preventing layer 40. The layers 4 and 5 can againboth consist of silicon nitride and the doping concentrations of thelayers 3 and 5 need not be different. However, it is required that thelayer 5 is thinner than the layer 3.

By means of a first masking and etching step, the layers 5 and 40 arepatterned (see FIG. 7A); this situation corresponds to that of FIG. 2A.Subsequently (see FIG. 7B), the silicon pattern obtained is converted bythermal oxidation at the edge into oxide 6. The nitride layer 40 and theexposed parts of the nitride layer 4 are etched away without a mask (seeFIG. 7C).

After etching away the oxide edges 6, the silicon of the layer 5 isconverted entirely by thermal oxidation into oxide 41, oxide layers 8being formed on the exposed parts of the layer 3 (see FIG. 7D). Thesilicon layer 5 must be so thin that the oxide layer 41 formed therefromis considerably thinner than the oxide layer 8. By selective etching,uncovered parts of the silicon nitride layer 4 are now removed, afterwhich the oxide layer 41 are etched away by a dip-etching step. A partof the oxide layers 8 is then maintained (see FIG. 7E). Subsequently,grooves are etched into the silicon layer 3 down to the oxide layer 2A(FIG. 7F). Since the same situation as in FIG. 2E is now obtained, themethod can be accomplished in the same manner as in the precedingexample (FIGS. 2E and 2F).

It will be appreciated that the invention is not limited to theembodiments shown herein, but that many variations are possible withoutdeparting from the scope of the invention. In particular, the inventionmay also be used in the manufacture of semiconductor devices other thanCCD's. Furthermore, the layer 2A may consist of an insulating materialother than silicon oxide, while the oxidation-preventing layers may havea composition other than that mentioned here. Of course, the clock andgate voltages required for controlling CCD's or SPS memories accordingto the invention may be varied according to desire by those skilled inthe art.

What is claimed is:
 1. A method of manufacturing a semiconductor devicecomprising a plurality of adjacent narrow and closely spaced coplanarsilicon electrodes, in which on an electrically insulating layer thereare deposited successively a first silicon layer, anoxidation-preventing layer and a second silicon layer, after which thesecond silicon layer is etched in a pattern comprising a plurality ofparallel silicon strips whereupon this silicon pattern is partlyoxidized and the uncovered parts of the oxidation-preventing layer arethen removed by etching, after which the oxide present is etched away,the second silicon layer and the uncovered parts of the first siliconlayer are thermally oxidized, the uncovered parts of theoxidation-preventing layer are removed by selective etching and apattern comprising parallel silicon electrodes separated by grooves isformed by etching away the subjacent parts of the first silicon layer,characterized in that at least two of the so formed silicon electrodeswhich are covered by the oxidation-preventing layer are interconnectedby means of a part of the first silicon layer, in that this connectionis interrupted by a masking and etching step, in that the uncoveredparts of the first silicon layer are thermally oxidized until thegrooves are filled at least in part with oxide, and in that byselectively locally etching the oxidation-preventing layer contactwindows are formed on the underlying silicon electrodes.
 2. A method asclaimed in claim 1, characterized in that the first silicon layer is ahighly doped layer and the second silicon layer is a considerably moreweakly doped layer.
 3. A method as claimed in claim 2, characterized inthat the first silicon layer is n-type conducting and has a dopingconcentration of at least 2.10²⁰ atoms/cm³.
 4. A method as claimed inany one of the preceding claims, characterized in that the secondsilicon layer is thinner than the first silicon layer, and in that asecond oxidation-preventing layer is deposited on the second siliconlayer, as a result of which the pattern formed from the second siliconlayer is partly oxidized only at the edge thereof, the secondoxidation-preventing layer being removed after this partial oxidation.5. A method as claimed in claim 4, characterized in that after etchingaway the oxide formed during the partial oxidation and removing thesecond oxidation-preventing layer, the second silicon layer is convertedentirely and the first silicon layer is converted only in part intooxide by thermal oxidation, after which by a dip etch the oxide formedfrom the second silicon layer is entirely, and the oxide formed on thefirst silicon layer is only partly removed.
 6. A method as claimed inclaims 1, 2 or 3 characterized in that the oxidation-preventing layerscomprise silicon nitride.